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To: kinkblot who wrote (3)	5/2/2000 6:30:00 PM
From: kinkblot	Read Replies (2) \| Respond to of 83

US Patent 6,020,252 issued 02/01/00 to Aspar et al. Method of producing a thin layer of semiconductor material patents.ibm.com Assignee: Commissariat À l'Énergie Atomique NOTE: LETI is part of the CEA, to which the patents are assigned. Rights are transferred to SOITEC, the commercial spin-off. From the background/summary of the invention: This invention has been conceived in order to improve the method described in FR-A-2681472 [~US-5374564]. After a step of ion implantation within a range of appropriate doses and before the separation step, it allows to carry out a thermal treatment of the part of the wafer corresponding to the future thin layer, in particular between 400° C. and 700° C. for silicon, without degrading the surface condition of the flat face of the wafer and without separation of the thin layer. This intermediate thermal treatment can form part of the operations for developing electronic components or can be applied for other reasons. This is done by implanting to an ion dosage level that is lower than in FR-A-2681472 but still sufficient to create microcavities. During a subsequent thermal treatment step the implanted gas atoms are precipitated and stabilized in the form of microcavities, such that the wafer is embrittled along the line of implantation, but not separated; there remain solid bridges across the region of microcavities. This method enables IC fabrication in the thin layer before lift-off & transfer, using standard thermal processing techniques. In particular, a thin layer with electronic circuits and components can be produced from a monocrystalline silicon wafer (subclaims 2 and 9). In that case, thermal annealing operations during IC fabrication can be carried out at up to 900° C. The thin layer is separated by application of mechanical force. WT

To: kinkblot who wrote (3)	5/5/2000 11:00:00 AM
From: kinkblot	Read Replies (3) \| Respond to of 83

SiGen Marches Forward electronicnews.com SiGen's NanoCleave process is a proprietary, implantation technology that it uses to cleave or separate the donor wafer from the device wafer along a plane that follows the atomic structure of the silicon. The company maintains that this results in a surface roughness that ranges between 4 and 8 Angstroms - less than 1 nanometer, according to SiGen. It is a significant step above typical hydrogen-induced thermal cleaving, which leaves a roughness of about 80 Angstroms, and in turn requires some sort of polishing or chemical etching. However, they may hit a brick wall: SOITEC registers a complaint against Silicon Genesis Corp. for infringement BERNIN, France, April 16, 1999. Today, SOITEC announced that it has filed a complaint with the United States District Court, for the District of Massachussetts, against the American company Silicon Genesis Corporation, for a patent infringement. SOITEC alleges that Silicon Genesis has infringed the US patent Nº 5.374.564 protecting the Smart Cut® process, for which SOITEC holds the exclusive world-wide license for all silicon applications. SOITEC seeks an injunction damages and interest, as well as the reimbursement of legal expenses. {SOITEC USA is located in Massachusetts} soitec.com The scope of SOITEC's Smart Cut® license from LETI is stated here. The assignee appearing on the patents is LETI's parent organization, Commissariat À l'Énergie Atomique. The Berkeley patent (US6027988) mentioned in the Electronic News article covers use of a particular implantation technique, plasma immersion ion implantation ("PIII"), which is claimed to have significant cost advantages over conventional beam line ion implantation. Over the last six months, SiGen has been awarded several U.S. patents related to 'their' Genesis Process, the first of which was: U.S. Patent #5,985,742 issued 11/16/99 to Henley and Cheung, Controlled cleavage process and device for patterned films patents.ibm.com sigen.com WT