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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (43166)	5/30/2000 2:20:00 AM
From: Tenchusatsu	Read Replies (2) \| Respond to of 93625

Carl, <The concept of "average latency" is a marketing buzz word created by Intel in an effort to try and move some of the RDRAM peak bandwidth advantage into the latency measurement. The whole idea is to fuzz up the latency definition with bandwidth, and then declare a victory on both latency and bandwidth.> No, the whole idea is to give a much clearer picture of latency than what the anti-Rambus coalition has been passing around as of late. It's not "marketing buzz," as you claim. Rather, it's a statement which acknowledges that latency is key to CPU performance, but also asserts that latency can indeed be affected by bandwidth (or a lack thereof). Unfortunately, most real-world benchmarks these days do not exercise peak bandwidth. This may be due to the P6 bus not running fast enough, among other factors. It may also be due to hardware advancing much faster than the demands of software today. In any case, this has worked in favor of the anti-Rambus coalition, who can then turn the word "latency" into a political buzzword. Like most FUD, it contains a grain of truth and a pound of bull. Tenchusatsu

To: Bilow who wrote (43166)	5/30/2000 3:12:00 AM
From: jim kelley	Read Replies (1) \| Respond to of 93625

Carl, Pale words of praise from a paid basher. It is curious that those who claim to be in possession of the facts are so prone to drawing the wrong conclusions.<LOL> Actually the post is my own, I do not copy without attribution. The "64 bit cache line access" is used many times in other posts. I have not checked its correctness but it does not matter to my argument. If the cache line is 256 bits my argument is stronger. If what you say is correct and the PIII has a 256 bit Cache line, then RDRAM average latency will be that much less than the initial latency. There will be 15 fast transfers and only one slightly slower transfer. This will be generally true although there will be occasional exceptions. INTEL did not have to create the notion of "average latency." It is an obvious concept. The same will be true for DRAM. As such it is not a "marketing buzz word ". Of course, the design of Tom's benchmark programs was focused on stressing "initial latency." They did this by using randomizing data references in a large array. This negated RDRAM's superior bandwidth in multiword transfers. This is what Scumbucket was attempting confuse mom and pop with in his earlier posts. The agenda is clear: Focus people's attention on a situation which is anomalous in computer programs. Programs have a great deal of locality. Data also has locality. Tom has created exceptions to these two principles. The lie is to say that these are normal conditions. Obviously, latency and bandwidth are related. If the test programs reduce the word transfer to one then RDRAM wil have a penalty relative to some SDRAM other things being equal. But this is not the normal state of affairs! As I said before, there is a lot of arrogance and cynicism being displayed in the attempt to confuse. This means there is great fear of RDRAM at AMD. Otherwise, why spend so much energy in this intense game of deception.