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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (115671)	6/13/2000 12:22:00 AM
From: Cirruslvr	Read Replies (3) \| Respond to of 1571806

Joe - RE: Cumine "T" Chuck said and Paul hinted there is a shrink for Cumine on the way. So this may be what "T" is. Also, either late last year or earlier this year there were rumors by Chuck and Paul, again, about a Cumine-512K, with obviously 512K L2 cache. Marc Hachman or Jack Robertson of the EDTN.com network needs to write an article detailing all this upcoming stuff for us. ;) The two Willys is still perplexing...

To: Joe NYC who wrote (115671)	6/13/2000 12:41:00 AM
From: Elmer	Read Replies (1) \| Respond to of 1571806

Re: "What do you think the Coppermine-T could be? New revision? A die shrink? Some kind of optimization? It looks like this will be some major revision of the core to find itself on the roadmap, but not too radical to earn a code name? Is there any room to for the .18u equipment to get to .15u or lower?" Jozef, Intel's .18u process started off with .13u channel lengths.... Re: "Suppose you do move the northbridge to the CPU. I guess there will be some savings in pins and some additional pins" If they moved the RMBS controller on-die there would no longer be a FSB..not likely. SMP would be impossible with Intel's current architecture. Re: "Suppose you do move the northbridge to the CPU. I guess there will be some savings in pins and some additional pins. You have add pins tor communication with AGP (piece of $hit), some communication with southbridge. I don't know what savings you could have. Can anyone come up with a ballpark figure of net addition of pins that migration of Northbridge to CPU would be?" You'd drop 64 bits (or would that be 128 <G>) for the databus and 32 bits for the addresses and control signals that are multiplexed on those pins plus a few more signals but you'd add some for the AGP port and a hublink for the south bridge but why not just drop this because it ain't gonna happen... EP

To: Joe NYC who wrote (115671)	6/13/2000 1:23:00 AM
From: THE WATSONYOUTH	Read Replies (1) \| Respond to of 1571806

Re: "What do you think the Coppermine-T could be? New revision? A die shrink? Some kind of optimization? It looks like this will be some major revision of the core to find itself on the roadmap, but not too radical to earn a code name? Is there any room to for the .18u equipment to get to .15u or lower?" I'll make a guess. Perhaps Intel optimized their 1.65V device a bit further allowing an additional 50A reduction in minimum channel length for an approx 7% improvement. They then combine this with an approx. 10% linear shrink ( about 20% area) to realize perhaps a total 15% speed improvement. This probably allows them a 1.2GHz bin split with minimum effort. They don't change the gate ox. or Vcc so as long as the new minimum device meets all other requirements, (Vt/Ioff/etc.) it's a drop in. A 10 percent linear shrink is easily achievable with the existing tool set and is likely not large enough to require an adjustment to film thicknesses. Also, the new device (if always shot small) will not break any ground rules and should fit in to the smaller area. This might be the easiest way to achieve a quick bump to maybe 1.2GHz. I expect Mustang will be a partial shrink as well. The ground rules AMD is using on Athlon and I assume on Thunderbird as well are NOT at all aggressive. In fact, the SRAM cell size is 5.95um2 which is surely larger than Intel even though AMD uses local interconnect which for similar ground rules allows for a 20% smaller cell size and perhaps a 15% increase in logic density. For instance, the SRAM cell in an IBM .18um process is about 4.3um2. So, I expect AMD to use this benefit more to their advantage with Mustang. Perhaps they are being overly conservative with Athlon/Thunderbird. all speculation THE WATSONYOUTH

To: Joe NYC who wrote (115671)	6/13/2000 1:41:00 AM
From: Hans de Vries	Read Replies (1) \| Respond to of 1571806

Jozef, What do you think the Coppermine-T could be? New revision? A die shrink? Some kind of optimization? It looks like this will be some major revision of the core to find itself on the roadmap, but not too radical to earn a code name? Is there any room to for the .18u equipment to get to .15u or lower? I think it is mainly a reaction to the 200/266 EV6 FSB of the Athlon. It seems that it will have a lower voltage (1.2V) GTL FSB which then would run at 200 (266?) MHz. There will be process-improvements without doubt but going to 150 nm is less likely in my opinion since they do mention the 130 nm products by name but don't say anything about 150 nm. Do you have any theory on Willamette 423 vs. 479? It's obvious that the change is there to enable it to work with Tulloch chipset. What do you think about my theory that Willamette 479 will have a built in Northbridge? This was my first idea as well. The memory interface belongs on the processor die. The current Willamette has 436 pins (Yes, I counted them from a photo...) An Integrated northbridge would hook them to Rambus however. They may preach the Rambus gospel but they will commit the DDR SDRAM sins secretly without a doubt... It would not surprice me at all if Camino3 and Almador are really the same die in different (Flip-chip) packages! This would resolve the impossible question of how many of each need to be produced. The same may be true for Tulloch... Regards, Hans