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To: Scumbria who wrote (2848)	7/29/2000 2:50:37 PM
From: Jim McMannis	Respond to of 275872

RE:"though it appears that Intel may have deepened the pipe past optimal on Willy (28 stages.)" So clock for clock Willy could be slower on a lot of benchmarks vs Athlon and coppermine? Break out the new benchmarks? <G> Willystone 2001? Jim

To: Scumbria who wrote (2848)	7/29/2000 9:07:36 PM
From: EricRR	Read Replies (2) \| Respond to of 275872

Generally speaking, a deeper pipe produces more MIPS, though it appears that Intel may have deepened the pipe past optimal on Willy (28 stages.) Where did you here 28 stages? I thought it was 20. Also you said in another post that the double pumped ALU was a big mistake because it prevents higher frequencies. Wasn't the double pumped ALU needed to prevent pipeline stalls?

To: Scumbria who wrote (2848)	7/31/2000 3:53:58 AM
From: Petz	Read Replies (1) \| Respond to of 275872

Scumbria: <Intel may have deepened the pipe past optimal on Willy (28 stages.)> Is there a chance that the Willy's seen so far have a poorer branch prediction algorithm than the Willy's that will be shipped? That would skew the benchmark scores significantly. Paranoid Petz

To: Scumbria who wrote (2848)	7/31/2000 5:10:36 PM
From: Saturn V	Read Replies (1) \| Respond to of 275872

Ref <Longer pipelines deliver higher clock rates, though there is an optimum length after which you start getting diminishing returns. The penalty for a longer pipe is fewer instructions executed per clock. The reason for this is that events which cause the pipeline to flush (branch misprediction, interrupts, etc.) take longer to recover from with a deeper pipeline, resulting in a lower average IPC (instructions per clock.) Performance is measured in MIPS (millions of instructions per second.) This is calculated as: instructions/second = instructions/clock * clocks/second Generally speaking, a deeper pipe produces more MIPS, though it appears that Intel may have deepened the pipe past optimal on Willy (28 stages.) > I think your post is a combination of DENIAL and WISHFUL THINKING. Didnt Intel state in February that Willamette has a better branch prediction capability than the PIII. Thus the number of pipeline stalls will be fewer than you estimate. Furthermore you have also forgotten the double pumped ALU. A lot of simple integer operations will execute in fewer cycles. The exact extent of the improvements will only be known a few weeks prior to first shipments. However I do not expect the Pentium 4 to underperform the Pentium III in instructions per clock. A few more weeks we all learn the exact performance of the Pentium 4. And I am certain that the results will be a lot better than you make it out to be.