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To: Daniel Schuh who wrote (21668)	12/6/2000 12:51:43 PM
From: nixtox	Read Replies (2) \| Respond to of 275872

Dan, If all that's needed is a thin layer, could that be related to the ion implantation machines that were (are)installed in the dresden building addition (clean room)? Nick

To: Daniel Schuh who wrote (21668)	12/6/2000 1:06:35 PM
From: andreas_wonisch	Read Replies (1) \| Respond to of 275872

Dan, Re: I'm really beginning to wonder about Andrew Thomas and this Isonics deal. One explanation is that he has a "real" source here and is milking it to the death. That would be, of course, the best-case scenario. It could be true since AMD is very tight-lipped about Palomino. Another explanation is that Thomas could have a financial interest in Isonics -- and just wants to hype the stock. But since this is illegal under UK law, he is either plain dumb (not so unlikely) or there is more behind this rumors. Andreas

To: Daniel Schuh who wrote (21668)	12/6/2000 2:30:42 PM
From: Ali Chen	Read Replies (1) \| Respond to of 275872

Dan, <Si28 line...now that it's just an epitaxial layer> On a second thought, the actual heat-generation area is the transistor's sub-micron channels. Even if the layer is 1um, it is still like a half-infinite space as compared to the channel size. Therefore if the 40% increase in thermal conductivity is true, this layer would really help to spread the heat and reduce peak temperature of individual transistors. So, it may be something into it. The only one thing that bothers me is the quality of the ISON published materials - no data, no numbers, just blurb - somebody "modelled" and "told" them... Pretty sad. Regards, - Ali

To: Daniel Schuh who wrote (21668)	12/6/2000 2:31:40 PM
From: Bill Jackson	Read Replies (2) \| Respond to of 275872

Dan, I can see the better heat dissipation helping the parts they have now. I can also see design improvements helping as well by cutting the heat made at source with lower Voltages, thinner gates and copper interconnects. So the path is very diverse. The highest speed parts might make use of solid Si28 wafers and a full redesign to smaller gates, lower volts etc. I have seen photos made in the infrared of CPUs in operation. They show the presence of hot spots and hot areas that have to do with power traces as well as with areas of intense gate switching. In fact such images are used to detect hot apots so the design team can minimize them by design. Hotspots are brain aneurisms, get too much pressure and an aneurism can pop and you have a stroke and might well die on the spot(as happened to a friend of mine at a lunch meeting). Well a hot spot can exist for a while and the Silicon in it is subjected to accelerated diffusion and this means that the characteristics of the transistors that are switching in the hot spot change bit by bit. After a while they change too much and the chip has a 'stroke'. Could be in memory and it will corrupt data or in another spot that stops execution that cycle. So cooling of hot spots with a Si28 epitaxial layer could allow the chip to operate without that failure mechanism killing it. Now to make it run so your hand can rest on the CPU?? that needs a high mass flow rate of air as well as excellent thermal coupling from the Si substrate to the copper spreader(it is pretty much certain that copper spreaders will be needed for the top performing heat sinks) through the use of very thermally conductive pasteIsilver) as well as an extremely small gap between the heat sink and the CPU. If this is done it is quite possible to get a fairly low temperature on the heatsink/CPU. Going further and using solid Si28 wafers will help this process, even more, however pure Si28 might be very pricey as it is made by gaseous diffusion or mass spectrographic methods that use a lot of electricity. Someone quoted a cost of about $10 per die....was that solid or epitaxially over plated? This may mean that only the very fastest premium parts will use the solid Si28 wafers. Bill