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To: Dan3 who wrote (126523)	2/3/2001 2:56:46 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Blow Hard Dan - Re: "8 900MHz CPUs sharing a single 100MHz memory bus? Ouch! I think I see a serious bottleneck here" You do? NEC doesn't. Compaq doesn't. Dell doesn't. IBM doesn't. Hewlett Packard Doesn't. Show us some DATA - Blow Hard Dan. Paul

To: Dan3 who wrote (126523)	2/3/2001 2:57:39 PM
From: Paul Engel	Respond to of 186894

Blow Hard One - Re: "Intel is extremely lucky AMD hasn't been able to ship its 266MHZ memory bus systems with point to point architecture. Intel dodged a bullet there, didn't they? " Nope - AMD just shot themselves in the head - AGAIN ! Paul

To: Dan3 who wrote (126523)	2/3/2001 3:14:06 PM
From: Paul Engel	Read Replies (1) \| Respond to of 186894

Blow Hard Dan - Re: "8 900MHz CPUs sharing a single 100MHz memory bus? Ouch! I think I see a serious bottleneck here" Nope - you're such a Blow Hard one that you IGNORE the significance of the 1 and 2 MegaByte L2 caches On-CHIP for the 700 and 900 MHz Xeons - that alleviate much of the external bus traffic. Now, Blow Hard Boy - why don't you tell us all about AMD's great success with their 2 MegaByte L2 MuSKANK ? Did you forget AMD's MUSKANK, Danny Girl? In case you forgot - AMD CANCELLED it !!! Another AMD self-inflicted wound to the head ! Paul

To: Dan3 who wrote (126523)	2/3/2001 3:17:57 PM
From: Paul Engel	Read Replies (2) \| Respond to of 186894

Blow Hard One - Re: "If (looking unlikely, I suppose) AMD ever ships SMP Athlon systems, they will dramatically outperform Intel's old clunkers." In one sentence you admit AMD won't even ship SMP systems and in the same sentence you claim that IF THEY do, they will outperform Intel's SMP systems !! Duh !!! You need a DOSE of REALITY !!! AMD has DROPPED any PRE-TENSE of shipping anything but 2-WAY ATHWIPER systems !!! And because of PERFORMANCE and RELIABILITY ISSUES, AMD is UNABLE TO ship even 2-way systems !! You live in your own universe, Monica Blow Hard Girl !!! Better get out from under Slick's Desk. Paul

To: Dan3 who wrote (126523)	2/3/2001 6:38:42 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 186894

Dan, <100MHZ FSB? In a machine that's expected to deal with mulitple processors on a shared memory bus? 8 900MHz CPUs sharing a single 100MHz memory bus? Ouch!> There are two FSB's in an 8-way Xeon system. Plus, when you've got 2M of cache on each processor, the high processor-to-bus clock ratio isn't that big of a deal. Don't you wish AMD could make any processor with more than 256K of cache? But hey, I guess if AMD can't make it, no one really needs it, right? Tenchusatsu