Re: if JC's rumor is true that Intel's DDR SDRAM Brookdale chipset will come out in October.
The first consideration is that if the chipset comes out in October, PC's using it won't appear in any volume until Q1 2002.
Beyond that, Intel would still need several other things to fall into place to present a threat to AMD. Unless they are fully ramped in 2 FABs at .13 for P4, they are capacity constrained. Since the first P4s on .13 will just be coming out in this time frame, P4 in Q4 should be a .18 product. Intel was limited to about 40 million Celeraon/P3's with its .18 capacity. So, right now on .18, if they produce no Celerons or P3s, they could produce about 10 million P4s per quarter. They will probably refine and upgrade their .18 process somewhat, so that should be up by at least 25% for Q4 (12-14 million if 100% of .18 capacity is used).
The wild card is the .13 copper FABs Intel is trying to bring on line, and the SOI process AMD is trying to bring on line. Intel claims to be targeting a very aggressive feature size and aspect ratio for their .13 and they have zero experience with high volume copper production. But they also have a good track record for production (though recently, that's slipped), and they have a lot of resources to throw at the problem. Two large .13 FABs would just about double Intel's total CPU production capacity. Celeron/PIII (as Tualatin, etc.) should be very small on .13. If Intel can get the equivalent of a half FAB online by August or September, out of the two being built, they could probably produce as many 1GHZ Celerons and 1.26GHZ PIIIs for Q4 as they can sell (say, 20 million combined, in Q4). Then Intel could use its .18 capacity to produce 12 to 14 million P4s in Q4, giving a total processor output of around 35 million units, and not leaving much room for AMD and VIA.
But a ramp of a new process that quickly would be unprecedented. It would be amazing if they could move all Celeron/PIII production to .13 and convert all .18 production to P4 that fast - I just can't see that happening. Remember, Intel has yet to produce a retail CPU using a copper process.
Why not use .13 for P4 and .18 for Celeron/PIII? Particularly for a large die chip, yields are much better on a smaller process. Why has Intel said that .13 would be reserved for the older core this year? Celeron/PIII is not going to be viable on .18 for Q4, while P4 is. AMD will be selling GHZ+ Durons in Q4 for very low prices, and Intel wouldn't be well served by having nothing but .18 Celerons/PIII to go up against Duron. Intel's strategy of using the early .13 wafers for Celereon/PIII makes sense.
On the AMD front, we have this very interesting tidbit from, of all sources, HP:
At the conference, HP R&D project manager Li-Ching Tsai delivered a presentation on a functional PA-RISC built on a seven-layer copper, 0.18-micron SOI process that runs at 980 MHz at 1.5 volts. The device has been tested to run at 1,030 MHz when set at higher voltages, said Tsai.
Architecturally, the PA-8700 is almost identical to a 600-MHz PA-RISC processor that HP described last year at the same conference. A significant exception is the cache size, which was increased by 50 percent, to 2.25 Mbytes.
The SOI process is said to have let HP raise the memory speed from 500 to 900 MHz and shrink the SRAM die size 34 percent, to 306 mm2. The cache dissipates 7.1 watts at 1.5 V.
aceshardware.com
AMD's wildcard is SOI. Intel has been trying to minimize the importance of SOI with research that shows that a .10 or .07 process using very low-K doesn't benefit from SOI. While that may very well be true, .13 and .18 processes using moderate K materials seem to gain substantial benefit from SOI. The speed benefits from moving to the Palamino core are another wildcard. Between SOI and Palamino, AMD should be able to stay close to P4 clock speeds at a given process size.
As there are more P4 and Palamino parts with overlapping clock speeds on the market, any IPC differences will become very clear. The market has responded to blatant IPC differences in the past - the early Celerons are the best examples of this. There appears to have been some recognition of the issue for P4, but only a little so far. Since there haven't been any real comparisons of, say, 1.5GHZ P4 to 1.5GHZ Palamino, any IPC comparisons represent extrapolations and editorials - that will have changed by Q4.
You were considering what would happen if Intel had a high volume of 2GHZ P4s while AMD was limited to 1.5GHZ. Bad for AMD, but very unlikely - even liquid nitrogen has only brought P4 to 2.1GHZ, so far. Equally unlikely, but barely possible, are high volume SOI/Palaminos at 2GHZ while P4 is limited to 1.7GHZ and that at a lower IPC.
Bottom line is, if either company screws up (Intel with .13/copper transition or AMD with SOI/Palamino transition, the company that doesn't screw up will find itself in a very good position. IMHO, what's most likely is that both will enjoy moderate but not complete success, and the situation will remain pretty much as it is: AMD making small market share gains as it sells comparable processors for 2/3s the price of Intel's equivalent processors.
Regards,
Dan |
