SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?


To: Scumbria who wrote (33816)3/27/2001 6:22:11 PM
From: PetzRead Replies (2) | Respond to of 275872
 
Scumbria, re:"There is no inherent penalty to a long pipeline." y(n+1)=2*y(n)+b*y(n-1)+x(n) Tell me how a pipeline longer than about 3 intstructions helps at all with that.

Petz



To: Scumbria who wrote (33816)3/27/2001 6:24:01 PM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Scumbria: There is no inherent penalty to a long pipeline. If branch prediction is perfect, the pipeline length does not affect IPC, yet allows for much higher clock rates.

Yes, but how was the branch prediction of the Cyrix chip? (didn't we just have this BPU discussion yesterday? ;)).

There are other problems with a longer pipeline as well. Instruction throughputs are, ideally, not affected, but latencies are. In the real world, instruction throughputs would seem to be affected to some degree as well - at least if you want to keep the die-size down.

-fyo



To: Scumbria who wrote (33816)3/27/2001 6:38:14 PM
From: Jim McMannisRead Replies (1) | Respond to of 275872
 
RE:"AMD would be wise to design a much longer pipe than they currently have."

Which chip?

Jim



To: Scumbria who wrote (33816)3/27/2001 6:42:24 PM
From: fyodor_Respond to of 275872
 
Scumbria: AMD would be wise to design a much longer pipe than they currently have.

It's cooooommmmiiiinnnnng!

;-)

-fyo



To: Scumbria who wrote (33816)3/27/2001 7:05:29 PM
From: porn_start878Read Replies (4) | Respond to of 275872
 
I think one of the slides relating to hammer mentioned something like :

"Pipeline allowing aggressive clockspeeds"

I'm not very anxious regarding to hammer clockspeed. What I wonder is what they'll have to replace EV6 bus, which will become a major bottleneck soon. Even if it can be scaled up to 400 (which is dubitous), at what price PC3200 DDR SDRAM will sell for? look at the price of high end videocards.

What is your opinon of the future of the EV6 platform?

Max