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To: gnuman who wrote (72390)	5/9/2001 5:03:45 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi Gene Parrott; The third step doesn't appear at the controller, it appears at the second RDRAM output, the one that took over driving a '1' from the first one. Re: "But be my guest, analyze the timing diagrams and if you can see a way to create a third step I'll be interested in knowing." Oh come on. You've already admitted that you're rusty on the subject. I've already analyzed the timing diagrams, and since I'm in such a good mood today, what with Rambus finally getting the FRAUD label that I've been saying they needed for several years, I will go ahead and post the timing diagrams here. Re: "The transition from Zo/2 to Zo at the source after the transient wave has passed? (Again, you need to calculate distance in ps from the source you choose)." The impedances never change with time on the RSL bus. Therefore, there is no "delta" load impedance. I'm beginning to wonder about you. Re: "You need to understand ..." If you don't want me to make fun of your ignorance, do try and be a little more careful in your wording. Unlike you, I am not "rusty" in my understanding of how transmission lines work. -- Carl

To: gnuman who wrote (72390)	5/9/2001 6:25:52 PM
From: Bilow	Read Replies (2) \| Respond to of 93625

Hi Gene Parrott; Here's an example of the third step... In these diagrams, time increases down the page. The transmission line is shown with the controller on the left, and termination on the right, and with two RDRAM chips between them: 'C' = Controller "-" = transmission line 'A' = RDRAM chip "A" 'B' = RDRAM chip "B" 'T' = Termination resistor 't' = Time Time values are in ns. For convenience, I chose a time scale of 0.10ns per step, but that the third step does not depend on this selection will be obvious. (For the illustration shown, an actual bit time would be more like 20 steps or so. But since the 3rd step is an event that happens between one chip ceasing transmission and another chip turning on, its existence is not dependent on the time scale. It's duration, by the way, turns out to depend on how far apart the SDRAMs are, in ns. Code: '0' = 1.8V '1' = 1.4V '2' = 1.0V '3' = 0.6V Action, Read of a long series of one bits from "A" t(ns) C---A------B----T 0.0 00001000000000000 0.1 00011100000000000 0.2 00111110000000000 0.3 01111111000000000 0.4 21111111100000000 Note: "A" arrives at controller at 0.4ns 0.5 22111111110000000 0.6 22211111111000000 0.7 22221111111100000 0.8 22222111111110000 0.9 22222211111111000 1.0 22222221111111100 1.1 22222222111111110 1.2 22222222211111111 1.3 22222222221111111 1.4 22222222222111111 1.5 22222222222211111 1.6 22222222222221111 1.7 22222222222222111 1.8 22222222222222211 1.9 22222222222222221 2.0 22222222222222222 Note: Bus reaches steady state Action, "A" finishes reading a long series of ones t(ns) C---A------B----T 0.00 22221222222222222 0.10 22211122222222222 0.20 22111112222222222 0.30 21111111222222222 0.40 01111111122222222 Note: "A" turn off arrives at controller at 0.4ns 0.50 00111111112222222 0.60 00011111111222222 0.70 00001111111122222 0.80 00000111111112222 0.90 00000011111111222 1.00 00000001111111122 1.10 00000000111111112 1.20 00000000011111111 1.30 00000000001111111 1.40 00000000000111111 1.50 00000000000011111 1.60 00000000000001111 1.70 00000000000000111 1.80 00000000000000011 1.90 00000000000000001 2.00 00000000000000000 Action: "B" begins reading a series of ones: t(ns) C---A------B----T 0.00 00000000000100000 0.10 00000000001110000 0.20 00000000011111000 0.30 00000000111111100 0.40 00000001111111110 0.50 00000011111111111 0.60 00000111111111111 0.70 00001111111111111 0.80 00011111111111111 0.90 00111111111111111 1.00 01111111111111111 1.10 21111111111111111 Note: "B" arrives at C at 1.1ns 1.20 22111111111111111 1.30 22211111111111111 1.40 22221111111111111 1.50 22222111111111111 1.60 22222211111111111 1.70 22222221111111111 1.80 22222222111111111 1.90 22222222211111111 etc. Since "B" arrives 0.7ns (= 1.1ns - 0.4ns) after "A" arrives, we must start "A" 0.7ns later than "B" in order for their signals to arrive with the same phase at the controller. 3-volt step case. "A" drives long series of ones to the controller, then turns off and "B" takes over, driving a long series of ones. Example. I choose to end "A"s output at its nominal 1.25ns time, and turn "B" on at its nominal 1.25ns time. These times have to be converted to actual times by adding delaying "A" by 0.70ns Therefore, "A" actually turns off at time 1.95ns, while "B" actually turns on at 1.25ns. This leads to the following result: t(ns) C---A------B----T 1.15 22222222222222222 Note: "A" in steady state driving one 1.25 22222222222322222 Note: "B" begins driving one (3rd step) 1.35 22222222223332222 1.45 22222222233333222 1.55 22222222333333322 1.65 22222223333333332 1.75 22222233333333333 1.85 22222333333333333 1.95 22222333333333333 Note: "A" turns off output when 2.05 22222233333333333 3rd step "B" output reaches it. 2.15 22222223333333333 2.25 22222222333333333 2.35 22222222233333333 Note: C begins receiving one from "B" 2.45 22222222223333333 2.55 22222222222333333 2.65 22222222222233333 2.75 22222222222223333 2.85 22222222222222333 2.95 22222222222222233 3.05 22222222222222223 3.15 22222222222222222 -- Car