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To: muzosi who wrote (72442)	5/9/2001 11:27:57 PM
From: Scumbria	Read Replies (2) \| Respond to of 93625

Muzo, There are two serious problems with Verilog that I see. One is begin/end syntax. What kind of moron thought that up? The other is that this operator "<=" has two different meanings. (I guess that is OK for C++ hacks.) Scumbria

To: muzosi who wrote (72442)	5/9/2001 11:35:26 PM
From: Bilow	Read Replies (1) \| Respond to of 93625

Hi muzosi; Amen to all of that. I'm not exactly sure how the outfit I'm at now got dragged into VHDL instead of Verilog, but it's been so long that I've forgotten Verilog completely. Well maybe not completely. I seem to remember something about @posedge and Flipflops... Using RLOCs? You must be an "X" guy, unless Altera is supporting them now. (I like the Xilinx architectures, but prefer the Altera tools, mostly, except for the RLOC, which is hard to beat.) I prefer to do RLOCs in schematics, by the way, so that's what I do, then translate the schematic files into VHDL, and finally go through the ugly machine VHDL and pretty it up a bit. My big problem with VHDL is that it is one of those languages that is intended to be everything for everybody. -- Carl