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To: Elmer who wrote (139270)	7/15/2001 8:57:25 PM
From: dale_laroy	Read Replies (1) \| Respond to of 186894

>If I am correct that AMD cannot efficiently yield large L2 die, then consider the implications of the strategy you outline above. The 512K version will yield poorly and the fallout will sell as value processors. This means AMD cannot have it's performance leader also be the volume leader with it's higher ASPs. At the same time most of their "value" processors will be silicon hogs with higher cost than a dedicated small die and lower ASPs than the Premium version. Given AMD's yield handicap, frequency scaling problem and delayed .13u process, their best bet is to minimize die size across the board and give up hopes of competing at the highend where their K7 design is running out of horsepower anyway.< Doubling the size of the L2 cache would, at most, double the defect rate. Actually, if we were to assume that 29% of AMD's desktop Palomino processors were to have one or more defects that forces AMD to salvage them as mobile Morgan processors, this should be quite adequate to meet demand for mobile Morgan processors. Yet this would extrapolate to a 50% yield of good processors with 512KB L2 cache. With the shrink to 0.13-micron the yield of fully qualified 512KB Thoroughbred processors could far exceed 50% of the total shippable Thoroughbred processors, even assuming the defect rate of the 256KB L2 cache Palomino is high enough to justify salvaging mobile Duron processors.