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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: andreas_wonisch who wrote (57002)	10/3/2001 9:46:13 AM
From: fyodor_	Read Replies (3) \| Respond to of 275872

Andreas: The only thing that irritated me a little bit was Hans claim that the memory controller would not be integrated into the northbridge. I thought AMD had already confirmed that it would be integrated? (which could reduce latency significantly) Apparently, this feature will be saved for the Sledgehammer (and be the main difference?). It is something of a disappointment that the memory controller would not be integrated on-die for the regular (Claw)Hammer, as this would give a significant performance increase in all applications. To be honest, I had expected ClawHammer to be much more Athlon-like, with the integrated memory controller and 64-bit'ness as the main differences, with a host of smaller changes including: changes to the cache structure (inclusive L1/L2, greater bandwidth, lower latency L2), SSE2, better prefetching, minor changes to the functional units, possibly increasing latency slightly where needed, so as not to limit the operating frequency, and lastly some tweaking of the balance betw. execution and decode resources. By the looks of it, ClawHammer will be very different from Athlon, featuring a single-cycle latency L0 instruction cache, funky prefetching and speculation (and the equally funky forward collapse unit), etc. etc. etc. -fyo

To: andreas_wonisch who wrote (57002)	10/3/2001 10:41:15 AM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Andreas, According to the article, Sledgehammer would still have integrated memory controller. Couple of positive things (to offset the negatives) of not having the memory controller on board, just fairly high bandwidth of HT is that there could be chipsets which incorporate single channel memory interface for low end to multiple-channel interface for higher end. A low cost dual system would not need to be limited by having to add memory by increments = processor data path width x number of processors, but at any increment the chipset supports. Also, processor not being tied to a memory type / speed may be a positive. The negative side, significant memory latency reduction will not happen. It remains to be seen what the magic of various latency reducing prefetching schemes will do. Also, by having 2 different schemes, AMD is fragmenting its own market. There will be a need for 2 northbridge / seminorthbridge chipsets to support both clawhammer and sledgehammer. This fragmentation may in fact kill Sledgehammer in the marketplace. One thing that I found a little wierd is the 3 HT channels going into Sledgehammer + pins for local memory access. That means a lot more pins than the current CPUs. I wonder if an HT switch or wouuld not be more cost effective. This would make the CPU cheaper, and make it easy to implement a shigle CPU Sledgehammer system without a switch, n-way implementation of higher end systems with a switch. Joe PS: It looks like the hint that Kap dropped here yesterday (about higher IPC of Hammer) is consistent with Hans's speculation on his site.