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To: wanna_bmw who wrote (62809)	11/8/2001 12:45:16 AM
From: Dan3	Read Replies (1) \| Respond to of 275872

Re: the failure of Timna because Intel tried integrating the chipset onto the CPU Timna failed because they integrated a Rambus controller onto the CPU. Using Rambus for anything is dumb, but locking it in for a chip targeted at entry level systems (where cost control is critical) was downright idiotic, and the program had to be cancelled. In their defense, the visionaries at Intel were certain that Rambus would be in close to 90% of all new computers sold by the end of this year, in which case an entry level system dependent on Rambus would have been reasonable. Just like they are certain that the weird, slow, expensive IA-64 has a prayer of competing against the compatible, fast, and inexpensive Hammer design.

To: wanna_bmw who wrote (62809)	11/8/2001 12:49:41 AM
From: Jim McMannis	Read Replies (2) \| Respond to of 275872

RE:"Are you saying that you called the failure of Timna because Intel tried integrating the chipset onto the CPU, and you knew that this was a bad idea?" I knew that the logistics of integration would hold back the clockspeed relative to the stand alone Celeron/P-III core. Originally porting it to Rambus didn't help much either...as it was supposed to be an economical solution and Intel can't even push the P4+Rambus much less a slow Timmy w/rambus... Can you say MTH? BTW, here is a link to the graphics performance of the two nForce selections...the 220 and 420...seems I understated the performance in Q3 arena (640x480)...it is 106 and 72 fps respectively. This is astounding for onboard video and just a bit under the geForce2. anandtech.com Jim

To: wanna_bmw who wrote (62809)	11/8/2001 9:51:30 AM
From: combjelly	Read Replies (1) \| Respond to of 275872

"You do realize, of course, that AMD is doing the same thing with Hammer?" Nope. They are integrating the memory controller, a far different thing from the memory controller, video, sound, IDE, keyboard, mouse, etc. In addition, there is always the possibility of using an external memory controller that interfaces through HT...

To: wanna_bmw who wrote (62809)	11/8/2001 11:29:29 AM
From: dale_laroy	Respond to of 275872

>You do realize, of course, that AMD is doing the same thing with Hammer?< No, no, no! Timna integrated the graphics controller as well as the memory controller on the same die as the CPU. Integrating the memory controller, or even a memory controller plus frame buffer graphics controller as Cyrix did with the Media GX is a great strategy. Integrating the memory controller boosts performance at less cost in die space than increasing the size of the integrated cache(s). Integrating the a frame buffer graphics controller provides acceptable performance at minimal die space cost. Timna integrated the memory controller and the graphics controller. Even with the choice of DRDRAM, integrating the memory controller would have, by now, turned out to be a good idea due to the collapse of even DRDRAM memory. The performance boost from integrating the memory controller would be greater than from an equivalent amount of die space allocated to additional cache. Integrating a 3D graphics controller is boneheaded. It significantly increases die size while actually reducing performance relative to a discrete 3D graphics controller.