Kakan, Re: "11.3 A High Performance 0.13 µm SOI CMOS Technology with a 70 nm Silicon Film and with a Second Generation Low-k Cu BEOL, J.W. Sleight, P.R. Varekamp, N. Lustig, J. Adkisson*, A. Allen*, O. Bula*, T. Chou, W. Chu, A. Gabor, P. Jamison, M. Khare, L. Lai, J. Ellis-Monaghan*, K. Peterson*, S. Rauch, S. Shukla, P. Smeys, T.-C. Su, J. Quinlan*, A. Vayshenker, B. Ward*, S.Womack, E. Barth, G. Biery, R. Ferguson, R. Goldblatt, E. Leobandung, J. Welser, I. Yang and P. Agnello, IBM Semiconductor Research and Development Center, Hopewell Junction, NY and *IBM Microelectronics, Essex Junction, VT"
Where is AMD? These guys look like they are from IBM.
Re: "11.4 A High Density 0.10µm CMOS Technology Using Low K Dielectric and Copper Interconnect, S. Parihar, M. Angyal, G. Yeap, B. Boeck , D. Reber, A.Singhal, T. Van Gompel. B. Wilson, M. Wright*, K. Strozewski, D. Smith, T. Sparks, T. Stephens, F. Huang, R. Mora, L. Vishnubhotla, Y. Solomentsev, V. Arunachalam, A. Phillips, K. Junker, N. Ramani, M. Rendon, J. Molloy, K. McGuffin, A. Michel, R. Pena, D. Rose, J. Schmidt, M. Smith, M. Wilson, L. Terpolilli, P. Grudowski, Y. Jeon, J. Chen, P. Le, J. Sun, M. Hall, M. Woo and C. Lage, Motorola, Inc., Austin, TX and *Advanced Micro Devices, Austin, TX."
Ok, this has one person from AMD. LOL. <G>
Funny, I don't see anything about SOI. Nothing about .09u manufacturing, either. 9 metal layers, while simplifying routing, also add cost and time to manufacturing. Nothing revolutionary here.
wbmw
P.S. Still think the Pentium 4 has 70% of its die running on the "slow" clock? <G>
Message 16697376 |
