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To: wanna_bmw who wrote (150446)	11/29/2001 7:24:37 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

WBMW, his point is to "prove" that the decoder runs at half-speed. He's trying to create a situation where the trace cache would be missed a lot, thereby making the decoder the limiting factor. I don't see how his experiment will conclusively prove anything. But when you're on a FUD campaign, conclusive proof is irrelevant. Tenchusatsu

To: wanna_bmw who wrote (150446)	11/29/2001 7:30:18 PM
From: kapkan4u	Read Replies (3) \| Respond to of 186894

<So I finally see how clever your code is, but I don't see why you would bother asking me to use it as a benchmark, since it only proves that it is possible to engineer around performance as much as it is to engineer for it> I never claimed that this code is representative. The purpose of this code is to compare the performance of the PIII and P4 decoders to demonstrate that P4's decoder is running at half the clock. So If my thesis is correct a 1GHz PIII will beat 2.0GHz P4 because this code is forcing most work to be done in decoders. In addition I expect 2.0GHz P4 to be about 50% slower then 1GHz PIII because P4 has only one decoder. Yes this code is artificial, but no more so than the synthetic P4 memory bandwidth benchmarks that Intel proudly displays on every corner. Kap