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To: fyodor_ who wrote (69204)1/27/2002 9:40:58 PM
From: combjellyRespond to of 275872
 
"Whenever Hammer does sample, it will almost certainly be on .13µm bulk. There have been numerous reports of two Hammers, one on the bulk process, one on SOI."

Numerous reports of a bulk Hammer? I must have missed them...



To: fyodor_ who wrote (69204)1/27/2002 10:19:41 PM
From: ElmerRead Replies (2) | Respond to of 275872
 
Whenever Hammer does sample, it will almost certainly be on .13µm bulk. There have been numerous reports of two Hammers, one on the bulk process, one on SOI. The main problem would seem to be that a layout optimized for SOI is very different from one optimized for bulk Si…

Yes! It would make most sense to put the first version on bulk process to debug the logic and then move it to SOI. But without any process data how do they know what to expect in the way of process performance? How do you design for a process you know next to nothing about? This is a double wammy. Sure they'll run some SRAMs but that's not enough. The standard procedure is to use a non critical product to debug the process first. I don't see AMD doing this in time to meet current schedules.

The main problem would seem to be that a layout optimized for SOI is very different from one optimized for bulk Si…

I see the same problem.

EP



To: fyodor_ who wrote (69204)1/28/2002 4:34:03 AM
From: kapkan4uRead Replies (1) | Respond to of 275872
 
<Whenever Hammer does sample, it will almost certainly be on .13µm bulk. There have been numerous reports of two Hammers, one on the bulk process, one on SOI.>

And where did you read that? Can I see some links please.

Kap