Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (159629)	2/21/2002 2:05:33 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 186894

Elmer, those are great links. Thanks! wbmw

To: Elmer who wrote (159629)	2/21/2002 3:38:01 PM
From: Yousef	Read Replies (2) \| Respond to of 186894

Elmer, Re: "Paul - I just ran across a great site for IC manufacturing costs and other excellent data ..." These are good links and the wafer cost table and Murphy's defect density/yield calculations are CORRECT. It's interesting to do some "what ifs" with the defect density/yield calculator. My current information is that foundries at .13um with LowK are above a defect density of 1.0. Typically, Intel "certifies" their processes at a defect density of .25 d/cm^2. For a 1cm X 1cm die, this defect density difference is a factor of two in yield or good die per wafer. AMD is in for a long struggle with .13um LowK technology. There used to be a "wanna be" lawyer on this thread that predicted AMD using LowK at .18um ... Hahaha Make It So, Yousef