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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (80848)	5/28/2002 5:06:51 PM
From: wanna_bmw	Read Replies (1) \| Respond to of 275872

Re: Please go and learn that "invalidating" of a cacheline has nothing to do with "flushing" of the cacheline data, one does not imply another No, sorry, but you're wrong. "Flushing" and "invalidating" are the same thing, as long as a line is owned by a caching device (processor or I/O hub), but is not in modified state. If the line has been modified, it will get written back to main memory. It's a very simple concept, but not one that I enjoy explaining over to you time and again. If you learned it differently, that's just too bad. Different engineering circles can use slightly different terminology. It's the fundamentals that make the difference, and that's where you continue to have a problem. Re: On "other agent's" writes (the other agent meaning either a bus-mastering I/O device, or other CPU), the cacheline is not "flushed", it makes no sense whatsoever since the data will be overwritten anyway. Then what do you think happens when processor A owns a cache line that is not modified, and an I/O device writes to the same line in memory, huh? That is the situation that Ace's brings up. The I/O device will communicate with the I/O hub. The write buffer on the I/O hub will issue a read for ownership, which will snoop the processor bus, and retrieve the cache line from memory. The memory controller will issue a signal indicating that the snoop was successful, and it will indicate that processor A has a cache line in ownership state. That line would have to be flushed, or invalidated. If this doesn't happen, then you get stale data in processor A, which violates MESI protocol. You wouldn't be a very good engineer if you let that happen. Even worse, if the line were modified, it would have given another signal, which would also tell the memory controller to expect modified data to be written back. If this didn't happen, then there would be two cache lines in the system containing different data that both claim to have the newest data. Nothing gets overwritten here, Ali. You still have to follow the cache protocol, no matter what system you are designing. Re: Nice try, wanna. In that particular paragraph Ace's were talking about bustmastering I/O device, they do not have caches and do not do write-allocate Bullsh!t. Are you talking about some desktop system? What platform do you have in mind? I know for a fact that some platforms implement write caches on their I/O hubs, and I/O devices will be communicating through these hubs to the CPU. Your ignorance of these mechanics doesn't make you right. Re: Actually, it gives me more confidence in AMD Really? Are you in a flip-flop mood for today, or do you not remember this post? Message 17523271 wbmw