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To: Tenchusatsu who wrote (170456)8/31/2002 9:34:10 PM
From: Dan3  Read Replies (2) | Respond to of 186894
 
Re: I think it's the L1 caches, especially the trace cache, that is suffering from thrashing. When you have multithreading, you want your caches to be large and flexible

Athlon has a 128K L1, P4 has 8K plus the trace cache (equivalent of about another 8K). So Athlon's L1 is 800% the size of P4's L1, and Athlon has 50% more execution units and 88 rename registers (I don't know how many rename registers P4 has).

Of the two chips, the Athlon core looks like a far better candidate for hyperthreading.



To: Tenchusatsu who wrote (170456)9/1/2002 11:55:22 AM
From: Charles Gryba  Read Replies (1) | Respond to of 186894
 
Tench, Intel has demonstrated high density SRAM L2 caches that occupy unsually small die area. Why can't they use that technology to add a second L1?

C


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