To: Lizzie Tudor who wrote (4811 ) 1/7/2003 2:17:30 PM From: Proud_Infidel Read Replies (1) | Respond to of 25522 Litho delays pose problems at 65-nm node, warns Sematech CEO By Mark LaPedus Semiconductor Business News (01/07/03 01:35 p.m. EST) PEBBLE BEACH, Calif.--The shift towards sub-90-nm technologies could pose some new and major problems for IC makers, including a possible delay of 157-nm tools at the 65-nm (0.065-micron) node, warned the top executive of International Sematech here today. New and complex wafer-fab materials are also expected to present more challenges for chip makers at the 65-nm node as well, said Bob Helms, president and CEO of Sematech, the Austin, Tex.-based chip-making consortium. “There are some significant technical challenges at that node,” Helms said. As a result, “R&D partnerships [between chip makers] will be a critical wave of the present. With a few exceptions, companies cannot go it alone,” he said in a presentation about the challenges of sub-90-nm technologies at the Industry Strategy Symposium (ISS) here today. Sponsored by the Semiconductor Equipment and Materials International (SEMI) trade group of San Jose, ISS runs from Jan. 5-8 in Pebble Beach. Leading chip makers are expected to develop IC products based on the 90-nm (0.09-micron) node starting in late 2003 or early 2004. Vendors are also projected to move to the 65-nm node by 2005. By then, microprocessors are expected to run at 4-GHz in the first phase of the 65-nm node, but will increase to 6-GHz at the “half node” in 2006, according to Helms. One of the major manufacturing challenges to enable 65-nm designs is clear: lithography. Leading-edge IC makers are currently scrambling to get their existing 193-nm lithography tools up and running at the 90-nm node. The next-generation 157-nm tools are expected to process the critical layers at 65-nm, but there are some issues with these scanners. Researchers have found unsuspected high levels of intrinsic birefringence in the lens materials, which will severely affect lens design and images at the wafer level in 157-nm tools. Technical issues have already prompted tool makers to delay the introductions of their 157-nm scanners (see March 8, 2002 story ). At ISS, Helms dropped hints that 157-nm tools may not be ready--at least for the first phase of 65-nm production in the 2005 time frame. “The lithography challenges are fairly significant,” Helms said. “I think the litho roadmap is a little more aggressive than we can hit. If you want to have a low-risk solution in the first half [of the 65-nm node], then you'd better have 193-nm tools ready,” he warned. Helms also hinted that 157-nm tools could be ready for the second phase of the 65-nm node, which is expected in the 2006 time frame. But even these advanced scanners alone will not address the entire problem in 65-nm. “To pattern down at half the wavelength is a daunting challenge,” he said. “If you want to cheat the 'Mother Nature' of litho, you will have to focus on new materials.” Among the materials in play for the 90-nm node and beyond include silicon-on-insulator (SOI), strained-silicon, and others. “High-k is also coming,” Helms said. “It's going to be needed for lower-power devices,” he said. “New materials are the wave of the future,” he added.