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To: Elmer Phud who wrote (148651)	1/21/2005 1:48:54 PM
From: Rink	Read Replies (1) \| Respond to of 275872

Elmer, do you know if Smithfield is single or dual die? Regards, Rink

To: Elmer Phud who wrote (148651)	1/21/2005 1:58:57 PM
From: burn2learn	Read Replies (2) \| Respond to of 275872

Elmer just a few items to screw with you numbers. I'm thinking along what Doug has been posting recently. Assume these variables Btq high bin P4 parts suffer 30-40% Le loss. these are the die left over after defetcts considered and are testable. So a high bin P4 part = 256 DPW from your numbers 4280.6=256 GDO or ~$9.3. of these parts only some fraction make top bin (maybe 10-20% when times are good). Smithfield, if it is two die connected then since not BTQ they have LE (litho expose) loss ~1-2% of testable die. 428098 =419GPW at sort the real question is how do you connect the die. Can you match separate die on the wafer in such case (419/2)/2400 =$11.4 of course some die wont match and would be should as 3.0 gig parts. but if die have to be next to each other on the wafer you still get $11.4 but a mix of single core and dual core parts because not all die have functional die next them. On top of that I'm sure the die would have to be matched at some performance level to be a DC product. I think Intel has a better chance of getting more DC parts than top bin SC parts thus cost less to consumer. fatter sweet spot

To: Elmer Phud who wrote (148651)	1/21/2005 2:01:02 PM
From: AK2004	Read Replies (1) \| Respond to of 275872

Elmer re: So Perhaps my $10 estimate was pretty close, no? only if that $5.60 includes all of the fixed costs like fab, equipment, development, etc depreciation Does it? -AK ps fixed costs should be significantly higher than variable, no?

To: Elmer Phud who wrote (148651)	1/21/2005 11:01:12 PM
From: etchmeister	Read Replies (3) \| Respond to of 275872

I've run some numbers and here's what I get. Hi ephud That's exactly what I was looking for - my question 156 x 2 = 312 (assuming size = 2x) 312 GDPW versus 428 GDPW; is the difference strictly due because larger die causes more silicon real estate loss at the edge? (BTW: I must be the only fool on Silicon Investor that owns Micron because of their 6F2 technology :O( Did you calculate on your own or do you have S/W ? Since I'm looking from Capex point of view my two cents input is that they will need more equipment to realize similar output (SC versus DC); also additional layer of copper Please let me know (I'm very interested in this die size study) TIA