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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: James Yegerlehner who wrote (25525)11/5/1997 7:53:00 PM
From: Investor A  Read Replies (3) | Respond to of 1578528
 
James,

I have done Winstone97 benchmark on Cyrix MX-PR233 with L2 cache enabled and disabled. Even with the most efficient L1 cache architecture from Cyrix MX, the system performance difference could be greater than 10%.
exchange2000.com

In the following report, the OEM quoted that the performance difference between the L2 cacheless and cache PII could be less than ten percent. With Intel inferior memory architectures, do you believe that it is a correct statement?

Currently, the Pentium II processors are standard with 512 Kbytes of cache. VARs will see some slower performance from chips with no L2 cache, depending on the application being run. By removing the L2 cache on a Socket 7-designed motherboard, a processor's speed could be degraded by as much as 15 percent, said motherboard OEMs. But sources said the Pentium II without cache may be slowed down by less than 10 percent.
crn.com



To: James Yegerlehner who wrote (25525)11/5/1997 8:07:00 PM
From: Petz  Read Replies (3) | Respond to of 1578528
 
James, re: no L2 cache on Pentium II.

Anyone with a Pentium II want to try disabling L2 cache in the BIOS? Then try something compute-intensive like doing a real long search-and-replace in Word or recalculating last year's taxes. I'll try it on my K6 tomorrow.

I have a feeling that the L2 Cacheless PII is either misinformation by Intel or a very temporary problem until they build a PII with built-in L2 cache (Like AMD's K6-3D chips will have.)

One interesting thing about "SLIT 1" is that its only claimed that it is "electrically" compatible, i.e., that it can use the same chipset. Since they don't claim it, I expect that it is mechanically incompatible with SLOT 1..

Petz



To: James Yegerlehner who wrote (25525)11/5/1997 11:57:00 PM
From: Jim McMannis  Respond to of 1578528
 
RE: "All-
It will be interesting to see how the L2 Cacheless PII benchmarks. If the
performance is similar to that of PMMX's or K6, then the only reason I
can imagine for it is to try to obsolete socket 7 as fast as possible; the
the cost of PMMX is presumably lower."

I think you just about summed it up. Intel wants to put the death nail in socket seven and will go to about any length to do it.

Jim


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