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To: neolib who wrote (16096)	6/1/2016 9:15:12 PM
From: rzborusa	Respond to of 72367

>>AMD seems to have returned to a small die strategy to optimize cost and provide scalability. Going forward, I expect the high-end products will be multi-die solutions combined on interposer with HBM. No more huge die. >That would seem to imply yield problems at GF. Large die have to be tough on yields everywhere. What could be ideal is qualifying (pairs of) parts sympatico with MCM and having a large profitable disposal of all others. I think TWY has a pretty good grasp, I sure hope he is right.

To: neolib who wrote (16096)

6/1/2016 11:37:31 PM

From: fastpathguru

Read Replies (4) | Respond to of 72367

That would seem to imply yield problems at GF.

Or it would imply that AMD wants to maximize yield because it's a worthy goal in and of itself. Would it be more prudent to NOT worry about yields on their first 14nm device?

Why is nVidia not catching flack for Osbourning their own product line? Product transitions happen all the time.

Re: Polaris... I see AMD creating a scalable VR solution... $200 gets you in the door (with ~R9 390 level performance!), and another $200 takes you to the top of the heap, where the competition costs $500.

Is the complaint that a $200 card can't make money? The meaty midrange space has always been in the $150-$250 range. And AMD has ZERO competition here, just when VR is taking off.

I agree that eventually, VR will be satisfied by mobile... But IMHO AMD is doing exactly what's necessary to corner the "premium VR" provider.

Re: Zen... What is UP with the hand-wringing? All that's happened is A) it's still "on track", B) silicon is apparently "working", and C) it will be sampling within weeks. I for one was not expecting actual Zen benchmarks, but apparently, the lack thereof is wrist-slit-worthy...

Re: AM4... Part of me wants it to have been launched. The part of me that just bought an FX-8370/R9-390x/32GB-DDR3-2100 rig for my Vive is glad it didn't wait for AM4/Bristol Ridge/Polaris... I can let the new platform sort out a bit.

fpg

PS: Yes, it's freaking cool. :) Got my Steam Developer's account kicked off; Feels like when the iPhone and Android intro'ed: A brand-new, wide-open market that can and will take off in a million directions, and I want to be a part of it.

To: neolib who wrote (16096)	6/2/2016 7:30:42 AM
From: Vattila	Read Replies (1) \| Respond to of 72367

> [A small die strategy] would seem to imply yield problems at GF. Without more info, I think that is an overly negative view. As far as I understand manufacturing (and that is not far), a small die is good. It improves yields because it counteracts defect density, which increases as you go to smaller nodes. Hence, if you use a shrink to just add more transistors for the same die size, you will have poorer yields and higher cost. Add to that, on a new process you start at the bottom of the yield learning curve. All in all, it makes sense to start off with a small die on a new process. Interposer technology, an exciting IP in AMDs arsenal, is another driver towards smaller die, even when you want/need more transistors. The ideals for the transistor and routing differ on the various parts of todays SOCs, e.g. the implementation of AMD's current APUs is a compromise better suited for GPUs, not high-performance CPUs. And less demanding parts of the die, e.g. southbridge functionality, could presumably be produced cheaper on older nodes. With multi-die on interposer, each die can be small and use a process and implementation best suited to it. On the other hand, the links on an interposer will incur penalties relative to a monolithic die, so it is a trade-off as well. And interposer technology is still in its infancy, adding counter-acting difficulty and cost. However, if these can be overcome, it seems the right way to go for SOC and large-transistor-count devices, such as GPUs.