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To: Kirk © who wrote (52053)	4/4/1998 2:07:00 PM
From: Ali Chen	Read Replies (1) \| Respond to of 186894

Kirk, <Intel was much better than the industry norm at making good clean rooms> The biggest area on uP chips is cache. I believe both Intel and AMD use cache redundancy technique to increase yields, so your defect analysis may not be so straightforward. Regards, Ali

To: Kirk © who wrote (52053)	4/5/1998 9:04:00 AM
From: Maxwell	Read Replies (1) \| Respond to of 186894

Kirk: <<My understanding was that Intel was much better than the industry norm at making good clean rooms and keeping their machinery from causing defects and thus they have lowered this number from 5 defects per layer to something much to the envy of AMD (and others). I guess you are saying Intel isn't that much better than the industry norm?>> In class 1 cleanroom there is less than 1 defect/m^3. Latest fabs equiped with the best air filtration are cleanroom better than class 1. Thus Intel's latest fab clean room is no better than Siemen, Motorola, etc. world class clean room. Normally defects do not come from cleanroom but the processing equipments. Just about all the fabs buy equipments from the same vendors such as AMAT, NVLS, LRCX, TEL, CVC, etc. Thus everyone gets about the same defect during processing. What makes a company such as Intel better than the rest is engineering discipline. If engineers are disciplined and monitored their processing tools closely then they can prevent catastrophy and save wafers. This discipline can improve yield above the norm. Also as a hint, backend processes are dirtier than front end process. Front end process are considered processes defining the transistors ending at polygate etch. Backend processes defining all the interconnects. If your process is heavily backended then don't expect to see high yield. The more you process the lower the yield be. Maxwell