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To: Scumbria who wrote (27987)	7/7/1998 3:31:00 PM
From: FJB	Read Replies (3) \| Respond to of 33344

Scumbria, Come on. The evidence speaks for itself. Alpha was running at 600MHz on a pretty average 0.35um process. Intel's "best in the world" 0.35um process, which offered a printed gate equal or better to DEC's(both around 0.28 I believe), had the PII topping out at 333MHz. The reason for the huge speed gap is CPU architecture - end of argument. I wish Frank or Kash would chime in, since they are more expert these matters. I'll leave you with this quote which should sound very familiar to you: I think you are probably aware of the fact that there are many factors affecting clock speed, only one of which is process technology. Alpha has been running at very high clock speeds for years, largely due to the architecture/design style/methodology. Message 5075038 What's that quote, "Consistency is the hobgoblin of small minds". <VBG> Bob

To: Scumbria who wrote (27987)	7/7/1998 5:08:00 PM
From: Paul Engel	Read Replies (1) \| Respond to of 33344

Scumbria - Re: "I present an open challenge to all, to describe an x86 speedpath which can not be broken down into basic RISC-like logic. " The fundamental difference - and one that limits x86 speed - is the INSTRUCTION LENGTH. RISC processors nearly always have all instructions the same length - 32 bits for example. However, the original x86 architecture had variable length instructions - some had simple, one byte instructions and some instructions were as long as 4 bytes - possibly more. Hence, when data is read from memory in, for example 32 bit chunks (4 bytes), the instruction decoder cannot simply decode this as one instruction. It has to examine the individual bytes and determine if they represent 1, 2, 3 or 4 instructions. Only then can the instruction be decoded. For 32 bit Risc processors, with 32 bit (4 byte) instruction lengths, each chunk of 32 bits (assuming no byte-alignment problems in the instruction stream) can be decoded immediately. As Intel has refined the x86 architecture, it has attempted to clean up - as best as possible - the variable instruction length problems, but this is still a major factor limiting x86 speed. Despite that complexity, Intel has managed to implement newer x86 processors that are so fast that there are very few RISC processors that can match it in clock speed and integer performance. Floating Point performance, despite many Intel improvements, still falls short of several RISC CPUs. Paul