Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (40510)	10/31/1998 2:11:00 PM
From: RDM	Read Replies (3) \| Respond to of 1573691

Excuse me for being incomplete. When I said cache fill rate I meant the "L1 cache" fill rate. This the transfer between the "L2 cache" and the "L1 cache" which occurs through the bus in the K6-2 and within the chip in the K6-3.

To: Scumbria who wrote (40510)	10/31/1998 3:13:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1573691

<The key performance factor for Winstone type benchmarks is memory latency, which is rapidly become constrained by sram speeds for L1 and L2 hits. That is why we are starting to see designs (like K7) which have multi-cycle L1 latencies.> If the problem is memory latency, wouldn't the multi-cycle L1 latency of the K7 be a step backwards? That's why the oversized L1 cache of the K7 still mystifies me. Even Intel felt the need to add an "L0" cache to Merced in order to provide critical data at minimum latencies. Tenchusatsu