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Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Ali Chen who wrote (40572)	11/1/1998 6:48:00 PM
From: Elmer	Read Replies (2) \| Respond to of 1573691

Re: "EP, <The P2P bus is of very questionable benefit> You and your buddies at Intel seem to have missed one more inflection point in modern technology: the time for old "busses" is over! By applying the whole power of your deduction, you may find out that the EV6 P2P is NOT a BUS, it is POINT-TO-POINT connection, and EXTREMELY FAST, without any tracing/termination/anti-reflection tweaks (where the major system production cost sits). The busses/switches are going into SILICON, buddy, S-I-L-I-C-O-N, to spell out for you, where they can really do the intercommunication job, with greater potential for speed, and without Xeon's 2-to-4 scalability constipation." Ali, you're just getting more and more confused as time goes by. Your point about P2P not being a bus is correct, it is Point to Point, but you can't go from the processor to the chipset in silicon alone. The chipset will require additional pins and traces for each processor added to the system. Will there be 1 chipset for a single processor system, another for a 2 processor system and still another for a 4, 8 etc? This added pincount is very expensive. K7 is stuck with very high, expensive pincount, expensive chipsets possibly with multiple versions, and a virtually untestable BSB (unless AMD slows it down). All these problems go away for Intel. The Intel P6 bus has none of these problems. No expensive added pins needed for P2P. With large cache, the bus does not saturate below 4 processors and there is no limit in sight for the bus frequency. On die L2 means no need to test at full core speed which is rapidly becoming beyond the state of the art in manufacturing equipment. The on die L2 greatly reduces processor pin count, reducing packaging cost and equipment cost and increasing performance. The K7 however does have very nice foils. Perhaps some more ruffage in your diet might help loosen you up. EP

To: Ali Chen who wrote (40572)	11/1/1998 8:22:00 PM
From: Tenchusatsu	Read Replies (2) \| Respond to of 1573691

<You and your buddies at Intel seem to have missed one more inflection point in modern technology: the time for old "busses" is over! By applying the whole power of your deduction, you may find out that the EV6 P2P is NOT a BUS, it is POINT-TO-POINT connection, and EXTREMELY FAST, without any tracing/termination/anti-reflection tweaks (where the major system production cost sits).> Ali, tell that to Sequent. They seem to think that putting twenty processors on one bus is fine. Perhaps you can tell us how server OEM's are going to create 4-way K7 chipsets without adding a crossbar, thus adding additional latency. Do you think that one north bridge chip will support four P2P connections? Perhaps you can have two north bridges each supporting two P2P connections, but once again, cache coherency is going to require additional latency cycles. Or maybe the 4-way K7 will go for a non-uniform memory architecture. Ali, many engineers would disagree with your statement that the multiprocessor bus is old-fashioned compared to multiple P2P connections. It's just two different styles of designing server platforms. There are advantages and disadvantages to both. By the way, Intel decided that Merced should go onto an SMP bus. According to you, they must be out of their minds to put new IA-64 technology on an "old-fashioned" bus. Tenchusatsu