Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Politics : Formerly About Advanced Micro Devices -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (45574)	1/12/1999 10:35:00 AM
From: Kevin K. Spurway	Read Replies (3) \| Respond to of 1573682

Re: "It sounds like PII -> PIII is almost as big a step forward as K6 -> K6-2 was." K6 --> K6-2 was a bigger deal because in addition to the 3D instructions, K6-2 added support for 100 MHz bus speeds--an actual everyday performance increase. By the way, Tom's rant from yesterday is a joke: 1) He apparently doesn't yet know the new official name of KNI--indicating he's way out of the loop (confirmed by the lack of updates to his site lately). 2) He has a problem with AMD selling 66 MHz rated chips. Doesn't Intel do that with the Celeron? Aren't there a lot of people out there with socket 7 mobos that don't support 100 MHz bus speeds that might want a faster processor with SIMD? Moreover, it's not like AMD is selling these chips and claiming they work at 100 MHz. Sounds like someone at AMD snubbed Tom and he's annoyed. So he continues to kiss Intel's *ss. Kevin

To: Scumbria who wrote (45574)	1/12/1999 2:17:00 PM
From: Tenchusatsu	Read Replies (1) \| Respond to of 1573682

Scumbria, from the INTC thread: <No, my hope for K7 is based on the fact that it was intentionally architected for high clock rates. The 3-cycle L1 cache is a good example.> Are you sure that the oversized L1 cache on the K7 has a latency of three clocks? How do you know this? If that's the case, I wonder if that oversized L1 cache is going to be more of a liability than an asset to the K7. Even if it drastically reduces the amount of L1 misses, the slowness of L1 hits could be a problem. In comparison, I would guess that the P6's L1 cache hit latency is only one or two clocks, and the P6's pipeline is slightly longer than even the K7's. Anyone care to comment? Tenchusatsu