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To: Paul Engel who wrote (82181)	5/30/1999 10:40:00 PM
From: grok	Read Replies (1) \| Respond to of 186894

Re: <I have just found out that the Camino does have an SDRAM interface - it's called the Memory Translator Hub and it connects SDRAM to the RAMBUS port on the Memory Controller Hub.> The part about connecting sdram to the rambus port and all this Hub talk is baffling to me. Does this really mean that it can be used with either sdram or drdram or is there some funny business going on. If would be really cool if it supported both and supported them equally well. But that sounds too good to be true.

To: Paul Engel who wrote (82181)	5/30/1999 11:50:00 PM
From: Tony Viola	Read Replies (1) \| Respond to of 186894

Paul, So, it would appear that Intel should be able to offer the Coppermine with Camino and 4X AGP, UltrDMA66 and SDRAM of at least 100 MHz SDRAM. Thanks for sleuthing that out! So, is the 100 MHz vs. 133 MHz interface logically, i.e., gates, latches, timing different, or "just speed" different? Tony

To: Paul Engel who wrote (82181)	5/31/1999 1:27:00 AM
From: Cirruslvr	Read Replies (1) \| Respond to of 186894

Paul - RE: "I have just found out that the Camino does have an SDRAM interface - it's called the Memory Translator Hub and it connects SDRAM to the RAMBUS port on the Memory Controller Hub." Can I take it that since you went to the effort to find out whether or not SDRAM could be used w/Camino, RDRAM may actually be delayed? At least they have a "Plan B". "I do not know if it is PC133 SDRAM compliant." If it did, I think it would be like stabbing Rambus in the back.

To: Paul Engel who wrote (82181)	5/31/1999 2:15:00 AM
From: dumbmoney	Read Replies (1) \| Respond to of 186894

Intel has talked about a Rambus<->SDRAM interface chip before. Is this something different?

To: Paul Engel who wrote (82181)	5/31/1999 1:15:00 PM
From: grok	Read Replies (2) \| Respond to of 186894

Thanks to wsp on the rambus thread I've been reading through IBM's website on sdram and ddr. Here's a paragraph that sums up the non-rambus scenario for future memories: What Comes Next: DDR IBM is an active supporter of double data rate SDRAMs (DDR SDRAMs) and has announced a commitment to this product family at the device, module and system level. With DDR SDRAM and the associated modules (such as the 184-pin registered DDR DIMM), IBM and other major vendors are proposing clock speeds of 133 MHz, which will result in a doubling of the memory data bandwidth over PC133 (to 266 Mbps/pin). By continuing along this path, memory migration in these systems can occur in an evolutionary manner — providing a significant improvement in memory bandwidth at a significant reduction in risk vs. more revolutionary proposals. Further bandwidth improvements will result from the use of the successor to DDR, which is currently identified as DDR II. Definition of this product is well underway in JEDEC, and the introduction of DDR II will ensure a continuous improvement in memory bandwidth to meet the demands of future systems.