To: fingolfen who wrote (134994 ) 5/15/2001 4:18:37 AM From: dale_laroy Read Replies (3) | Respond to of 186894 >Honestly, I don't think that the design has those kinds of legs. I'm not sure how AMD is generating the speed bins they are at this point, but my guess is that they're pushing down gate length faster than Intel is at this point (at least until Intel transitions to 0.13 micron). That's great for the short-term, but takes all of the fire out of AMD's 0.13 micron transition.< Not really, it appears that AMD is anticipating that Thoroughbred will get to about 2333 MHz by the time Barton launches, versus 1.8 GHz for Palomino by the time Thoroughbred launches. Barton will then probably take Athlon all the way up to about 2833 MHz. > You may outrun a P4 today on a few select applications, but you won't be next year as more SSE2 software comes available (especially with the x87 performance increase people are discovering... see JC's).< It appears that Thoroughbred will implement SSE2+. Since AMD has mentioned SSE+ making an appearance before Hammer. > You're also assuming that both the K7 and P4 scale linearly and the slope of the K7's line is greater than that of the P4... which is a questionable assertion.< Not even Jerry Sanders believes this. His presentation indicates that even with SOI, Barton will not be as strong of a competitor versus Northwood as Palomino will be versus Willamette. Best guess is that Barton versus Northwood will be about the equivalent of TBird versus Willamette. >I don't think the Athlon will be able to keep up with the Northwood-P4's, and any market share that AMD gains will erode back to their traditional 15-18%. AMD has held as much as 25-30% in the past... and probably will again. Then Intel will take it back again.< AMD will probably reach 30% market share in Q3 2002, but after that the situation becomes very shaky. When Intel introduces the value segment P4, probably in early 2003, Athlon will be about as competitive versus P4 as Cyrix's MII was versus AMD's K6-2 at introduction, and the parallel should not stop at the introduction. Assuming Hammer lives up to my expectations, AMD can continue to compete against P4 using Fab30, but Fab25 will probably have to be converted over to flash. With just Fab30 producing processors, and the Hammer series being at larger die sizes than Athlon/Duron, AMD's market share could plunge to under 15% by the time Fab35 begins to ramp. >Looking to the future, AMD is going to become increasingly dependent on corporate welfare for fabs and processes. They simply don't have the money to develop their own processes and build all their own fabs like Intel.< Well, according to UMC, a company needs $8 billion in revenue per year to justify building a 300mm wafer fab. It looks like AMD may just manage to slide under the wire. As for 450mm fabs, it appears that only Intel will have the resources to be able to afford to build a 450mm fab solo. > Moto helped them out with a back end... now IBM is bailing them out with a front-end SOI process. Pretty soon AMD isn't going to be making CPU's on a process which in any way, shape, or form was originated by AMD.< AMD has never succeeded with a home grown process since the 0.7-micron process at the Submicron Design Center. So little will be changing as far as developing their own process technology. > Intel on the other hand "rolls it's own," and develops a new logic process in-house every 18 months.< Intel introduced their 0.18-micron process technology in June/July 1999. Their 0.13-micron process technology will be introduced no earlier than June/July 2001. This is a 24-month, possibly greater than 24-month, cycle. > As processes move to 300mm wafers, AMD is going to find itself further behind... I just don't see the long-term growth potential. AMD has always played to a niche market, and doesn't have the capacity to ever do more.< They may have the potential, but not within the scope of any of their currently announced plans. AMD needs to start with Hammer being able to keep up with P4's peak speed grade, then find capacity to replace Fab25 capacity as Fab25 is converted to Flash, then continue to add capacity right up to the beginning of the ramp at Fab35. One possible scenario for this would be to lease capacity at UMC's Fab12 until Fab35 is fully ramped. AMD might begin by leasing capacity at UMC's Fab12 at the rate of two 300mm wafer starts at Fab12 for every five 200mm wafer starts at Fab25 converted to flash, then continue leasing additional capacity until perhaps 2/3 of UMC's Fab12 capacity is leased at the beginning of the ramp at Fab35. AMD could then decrease the amount of leased capacity at UMC's Fab12 as capacity ramps at Fab35. > They are a legitimate competitor to Intel, which has pushed the CPU market forward faster than anyone expected... but they aren't in a position to dominate it, even if the Athlon was really as good as you seem to think it is...< AMD definitely has a snowball's chance in Hell of dominating with Athlon, but there is an outside chance that Hammer could enable them to dominate. A more likely scenario would be that AMD might achieve 30% market share with Athlon, temporarily lose it, then return to a 30% market share and keep it throughout the P4 processor generation. But even this is hardly a safe bet. >This is business. Intel has the capital, know-how, and resources to succeed in the long-term... This isn't "Jerry Skywalker" and the "Quest for the Speed Crown." It's not even a good mythos structure upon which to build fiction, much less base investment decisions.< No doubt about the capital, know-how, and resources part, but so did IBM at the time they attempted to force MicroChannel on the industry. The real question is, will the know-how be able to penetrate the layers of buracracy.