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To: dale_laroy who wrote (135066)5/15/2001 6:27:23 AM
From: pgerassi  Read Replies (2) | Respond to of 186894
 
Dear Dale:

You are under a mistaken impression. Intel is no longer in the process lead. AMD leads and Intel follows. Northwood is not going to make it against Throughbred on a performance basis. Barton would serve it up on a silver platter and the Hammers will grind it to dust.

Pete



To: dale_laroy who wrote (135066)5/15/2001 10:30:51 AM
From: Windsock  Read Replies (2) | Respond to of 186894
 
Dale - Re:"It appears that Thoroughbred will implement SSE2+. Since AMD has mentioned SSE+ making an appearance before Hammer."

Why is AMD so slow implementing SSE? It should take less time to develop when AMD is just copying SSE after Intel did all the heavy lifting developing the technology.



To: dale_laroy who wrote (135066)5/15/2001 11:51:34 AM
From: fingolfen  Read Replies (3) | Respond to of 186894
 
Not really, it appears that AMD is anticipating that Thoroughbred will get to about 2333 MHz by the time Barton launches, versus 1.8 GHz for Palomino by the time Thoroughbred launches. Barton will then probably take Athlon all the way up to about 2833 MHz.

What's your source??? I've seen no speeds even remotely resembling that on any roadmap.

It appears that Thoroughbred will implement SSE2+. Since AMD has mentioned SSE+ making an appearance before Hammer.

Implication: AMD will need it to compete with the P4. If it wasn't needed, why pay a hefty licensing fee to Intel to use it.

Not even Jerry Sanders believes this. His presentation indicates that even with SOI, Barton will not be as strong of a competitor versus Northwood as Palomino will be versus Willamette. Best guess is that Barton versus Northwood will be about the equivalent of TBird versus Willamette.

Of course that's how you present it... but using marketing to position one product against another doesn't make it a "strong...competitor."

Assuming Hammer lives up to my expectations, AMD can continue to compete against P4 using Fab30, but Fab25 will probably have to be converted over to flash. With just Fab30 producing processors, and the Hammer series being at larger die sizes than Athlon/Duron, AMD's market share could plunge to under 15% by the time Fab35 begins to ramp.

You underscore my point, but I disagree with the timeline. I think AMD's high point will be Q3 of '01. They won't have strong competition for Northwood, and the K8 series won't be out for another year. AMD will erode back to their traditional baseline of 15-18% market share by that time. By the time the K8 is out, who knows what Intel will have out...

Well, according to UMC, a company needs $8 billion in revenue per year to justify building a 300mm wafer fab. It looks like AMD may just manage to slide under the wire. As for 450mm fabs, it appears that only Intel will have the resources to be able to afford to build a 450mm fab solo.

Agreed... although I really wonder if Si technology as we know it now will make it to the 450mm generation. Probably will, but there will be major changes between now and then.

Intel introduced their 0.18-micron process technology in June/July 1999. Their 0.13-micron process technology will be introduced no earlier than June/July 2001. This is a 24-month, possibly greater than 24-month, cycle.

I can see your point there, but I don't think it's an apples to apples comparison. The first product released on 0.18 micron was a shrink of the mobile P2 die. It was placed into [very] limited release as a niche product. The first "real" 0.18 micron product was coppermine, which was not released until September/October '99 if memory serves. Tualatin is allegedly going to be a release far similar to Cu'Mine as opposed to the P2 mobile shrink. I guess we'll have to see what volumes come out in the first couple of weeks after launch. If it's a big launch, then it should be compared to the Cu'Mine launch date, not the P2 shrink date... (I know it's going to be more than 18 months in both cases, but it's a more valid comparison).

They may have the potential, but not within the scope of any of their currently announced plans. AMD needs to start with Hammer being able to keep up with P4's peak speed grade, then find capacity to replace Fab25 capacity as Fab25 is converted to Flash, then continue to add capacity right up to the beginning of the ramp at Fab35. One possible scenario for this would be to lease capacity at UMC's Fab12 until Fab35 is fully ramped. AMD might begin by leasing capacity at UMC's Fab12 at the rate of two 300mm wafer starts at Fab12 for every five 200mm wafer starts at Fab25 converted to flash, then continue leasing additional capacity until perhaps 2/3 of UMC's Fab12 capacity is leased at the beginning of the ramp at Fab35. AMD could then decrease the amount of leased capacity at UMC's Fab12 as capacity ramps at Fab35.

I still doubt it's going to be enough. AMD by contract can't foundry out more than 20% of its total volume. By the time AMD has 300mm capacity ramping, Intel will have a minimum of 3 ramped 300mm fabs. Intel will enjoy a 30% cost per die advantage on 300mm when compared to the same 200mm process. In this industry, 30% is HUGE. AMD is in the unenviable position of not being able to afford to move to 300mm, but at the same time not being able to afford NOT to move to 300mm.

No doubt about the capital, know-how, and resources part, but so did IBM at the time they attempted to force MicroChannel on the industry. The real question is, will the know-how be able to penetrate the layers of buracracy.

That's a good point. People like to characterize Intel as a big ship that won't move, but I think that's more "mythmaking and fiction" than reality. The semiconductor industry as a whole doesn't turn on a dime. "Nimble" AMD couldn't crank out the K7 and then the K8 two years later. It's going to take a minimum of 3 years to get out the K8 series, and I bet they'll probably slip another 6 months before they see the light of day. This begs the question, what is Intel working on to follow-up the P4????