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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: hmaly who wrote (84156)	7/4/2002 8:11:34 AM
From: Windsock	Read Replies (1) \| Respond to of 275872

Re:"Who are you trying to kid. All it takes is a couple of those Intel trained Taiwanese whiz kids to go back home and teach them everything Intel knows about process and more." If it is that easy why doesn't AMD go get a couple engineers that know how to make a 0.13 process work? And maybe a few from IBM that know how to make SOI work.

To: hmaly who wrote (84156)	7/4/2002 11:29:21 AM
From: semiconeng	Read Replies (1) \| Respond to of 275872

Who are you trying to kid. All it takes is a couple of those Intel trained Taiwanese whiz kids to go back home and teach them everything Intel knows about process and more. Who is to say there aren't a couple of Dirk Meyers working for Intel just chomping at the bits, just waiting for the right opportunity. Several times you have mentioned Intel getting first dibs on machines, but I can't believe process is a machine thing , but rather a personel thing; and personel can walk out the door. Not only that, there is always someone better than you out there, just itching for the right moment. I don't completely agree. Process Engineering is a "personal (personnel?) thing" only to a certain extent. The success or failure of Process Improvement, IS partially dependent on the Process that you have to work with. Certainly there are general Process Improvements that will scale across multiple Processes, but it is difficult enough to transfer Process Improvements from generation to generation, much less how difficult it would be to Transfer from one company's Process Equipment to another's. THAT'S the issue, not some ASIC/MPU thing. I don't think the ASIC/MPU issue is significant, IMO. That being said, If I were to drive across town to MOS12, and walk inside their Fab, I'm sure there would be SOME amount of Process Knowledge that could immediately apply to their Process, from General Knowledge of Semiconductor Processes, but If I was expecting MOS12's Process to equal the Process at another Site, I would be in for a disappointment. In my experience, It just doesn't happen that way. Close...... Maybe. Equal...... Doubtful. Better...... I don't see how. And it isn't going to be easy, there's allot of "variables" to overcome...... I think that was Yousef's point. Semi

To: hmaly who wrote (84156)	7/4/2002 5:30:30 PM
From: Petz	Read Replies (2) \| Respond to of 275872

A new theory on UMC Bartons: Recently info surfaced that Bartons will have a ModelHz rating about 1.5 times their clock speed and have 512K cache rather than 256. Then we saw info about their relatively low initial clock speed. I believe the reason for all this is that they will be the new Durons and their MHz will be compared to P4 Celerons. This eliminates the need to explain a big increase in IPC -- they are just being compared against much-slower-than-Northwood Celeron P4s. The lower-than-expected MHz is to be expected of a foundry process. Also, since MHz is limited by the process, it is a good tradeoff to add a little to the cost by increasing to 512K cache. AMD must be confident of decent yields and wants the majority of the Bartons to be considerably faster than the approx. 2 GHz Celerons that Intel will be selling in Q4. Petz